| 类型：放大器 | 用途：*** | 品牌：AD/亚德诺 |
| 型号：DAC8413AT/883C | 封装：法兰封装 | 功率：16W |
| 特色服务：通信 | 批号：16+ |
DAC8413AT/883C
Quad, 12-Bit DAC Voltage Output with Readback
SMJ320C40HFHM40
The C40 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.72-um, double-level metal CMOS technology. The 320C40 is a part of the fourth-generation DSPs from Texas Instruments and is designed primarily for parallel processing.
For additional information when designing for cold temperature operation
Key Features
SMJ: QML Processing to MIL-PRF-38535
SM: Standard Processing
TMP: Commercial Level Processing TAB
Operating Temperature Ranges:
Military (M) -55°C to 125°C
Special (S) -55°C to 100°C
Commercial (C) -25°C to 85°C
Commercial (L) 0°C to 70°C
Highest Performance Floating-Point Digital Signal Processor (DSP)
40 MFLOPS, 20 MIPS, 220 MOPS, 256 MBps
50-ns Instruction Cycle Time:
50 MFLOPS, 25 MIPS, 275 MOPS, 320 MBps
40-ns Instruction Cycle Time:
60 MFLOPS, 30 MIPS, 330 MOPS, 384 MBps
33-ns Instruction Cycle Time:
C40-60:
C40-50:
C40-40:
Six Communications Ports
6-Channel Direct Memory Access (DMA) Coprocessor
Single-Cycle Conversion to and From IEEE-745 Floating-Point Format
Single Cycle 1/x, 1/√x
Source-Code Compatible With SMJ320C30
Validated Ada Compiler
Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers
12 40-Bit Registers, 8 Auxiliary Registers, 14 Control Registers, and 2 Timers
IEEE Standard 1149.1 Test-Access Port (JTAG)
Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers:
High Port-Data Rate of 100 MBytes/s (Each Bus)
16G-Byte Continuous Program/Data/Peripheral Address Space
Memory-Access Request for Fast, Intelligent Bus Arbitration
Separate Address-, Data-, and Control-Enable Pins
Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware
Packaging:
325-Pin Ceramic Grid Array (GF Suffix)
352-Lead Ceramic Quad Flatpack (HFH Suffix)
324-Pad JEDEC-Standard TAB Frame
Fabricated Using Enhanced Performance Implanted CMOS (EPIC?) Technology by Texas Instruments (TI?)
Separate Internal Program, Data, and DMA Coprocessor Buses for Support of Massive Concurrent Input/Output (I/O) of Program and Data Throughput, Maximizing Sustained Central Processing Unit (CPU) Performance
On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance
512-Byte Instruction Cache
8K Bytes of Single-Cycle Dual-Access Program or Data RAM
ROM-Based Bootloader Supports Program Bootup Using 8-, 16-, or 32-Bit Memories Over Any One of the Communications Ports
SM320VC5507PGESEP 描述
The SM320VC5507 fixed-point digital signal processor (DSP) is based on the SMS320C55x DSP generation CPU processor core. The C55x? DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.
The 128K bytes of on-chip memory on 5507 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or more on-chip memory but less than 128K bytes of memory, and need to operate in standby mode for more than 60% to 70% of time. For the applications which require more than 128K bytes of on-chip memory but less than 256K bytes of on-chip memory, Texas Instruments (TI) offers the TMS320VC5509A device, which is based on the TMS320C55x DSP core.
The general-purpose input and output functions and the10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media is supported through three McBSPs.
The 5507 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include Universal Serial Bus (USB), real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5507. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.
The 5507 is supported by the industry’s award-winning eXpressDSP?, Code Composer Studio? Integrated Development Environment (IDE), DSP/BIOS?, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX?, XDS510? emulation device drivers, and evaluation modules. The 5507 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.
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