SMJ320C31GFAS60成都高端ICqorvo放大器 鸿科伟业现货详细介绍

SMJ320C31GFAS60

The SMJ320C31, SMJ320LC31, and SMQ320LC31 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.6-?m triple-level-metal CMOS technology. The devices are part of the SMJ320C3x generation of DSPs from Texas Instruments.

The SMJ320C3x internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 60 MFLOPS. The SMJ320C3x optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.

The SMJ320C3x can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are results of these features.

General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The SMJ320C3x supports a wide variety of system applications from host processor to dedicated coprocessor.

High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

SMJ320C31GFAS60

Key Features

• Processed to MIL-PRF-38535 (QML)

• Operating Temperature Ranges:

• Military (M) -55°C to 125°C

• Special (S) -55°C to 105°C

• SMD Approval

• High-Performance Floating-Point Digital Signal Processor (DSP):

• SMJ320C31-60 (5 V) 
  33-ns Instruction Cycle Time 330 Million Operations Per Second (MOPS), 60 Million Floating-Point Operations Per Second (MFLOPS), 30 Million Instructions Per Second (MIPS)

• SMJ320C31-50 (5 V) 
  40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS

• SMJ320C31-40 (5 V) 
  50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS

• SMJ320LC31-40 (3.3 V) 
  50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS

• SMQ320LC31-40 (3.3 V) 
  50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS

• 32-Bit High-Performance CPU

• 16-/ 32-Bit Integer and 32-/ 40-Bit Floating-Point Operations

• 32-Bit Instruction and Data Words, 24-Bit Addresses

• Two 1K Word × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks

• Boot-Program Loader

• 64-Word × 32-Bit Instruction Cache

• Eight Extended-Precision Registers

• Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)

• Two Low-Power Modes

• On-Chip Memory-Mapped Peripherals:

• One Serial Port Supporting 8-/ 16-/ 24-/ 32-Bit Transfers

• Two 32-Bit Timers

• One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation

• Fabricated Using Enhanced PerformanceImplanted CMOS (EPIC?) Technology by Texas Instruments (TI)

• Two- and Three-Operand Instructions

• 40 / 32-Bit Floating-Point / Integer Multiplier and Arithmetic Logic Unit (ALU)

• Parallel ALU and Multiplier Execution in a Single Cycle

• Block-Repeat Capability

• Zero-Overhead Loops With Single-Cycle Branches

• Conditional Calls and Returns

• Interlocked Instructions for Multiprocessing Support

• Bus-Control Registers Configure Strobe-Control Wait-State Generation

• Validated Ada Compiler

• Integer, Floating-Point, and Logical Operations

• 32-Bit Barrel Shifter

• One 32-Bit Data Bus (24-Bit Address)

• Packaging

• 132-Lead Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix)

• 141-Pin Ceramic Staggered Pin Grid- Array Package (GFA Suffix)

• 132-Lead TAB Frame

• 132-Lead Plastic Quad Flatpack (PQ Suffix)

SM320VC5507PGESEP 描述

The SM320VC5507 fixed-point digital signal processor (DSP) is based on the SMS320C55x DSP generation CPU processor core. The C55x? DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 128K bytes of on-chip memory on 5507 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or more on-chip memory but less than 128K bytes of memory, and need to operate in standby mode for more than 60% to 70% of time. For the applications which require more than 128K bytes of on-chip memory but less than 256K bytes of on-chip memory, Texas Instruments (TI) offers the TMS320VC5509A device, which is based on the TMS320C55x DSP core.

The general-purpose input and output functions and the10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media is supported through three McBSPs.

The 5507 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include Universal Serial Bus (USB), real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5507. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.

The 5507 is supported by the industry’s award-winning eXpressDSP?, Code Composer Studio? Integrated Development Environment (IDE), DSP/BIOS?, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX?, XDS510? emulation device drivers, and evaluation modules. The 5507 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

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